搜索资源列表
VHDL-FPGA-clock
- FPGA数字钟的设计,用VHDL语言编程,max+plus仿真,可在实际电路中验证-FPGA design, VHDL programming, max plus simulation, in the actual circuit verification
dzzh
- eda课程设计:数字钟--vhdl语言全部源代码
VHDL
- VHDL数字钟 数字电子钟 此数字电子钟具有的功能包括: 1. 计时,时、分、秒显示; 2. 十二小时与二十四小时之间的转换; 3. 上下午显示; 4. 对时、分、秒的校时功能;
duogongnengdianzishuzizhong
- 多功能电子数字钟vhdl 计算机专业课程设计必备
CLOCK
- 可以调整时间和设置闹钟的数字钟(VHDL)
VHDL学习的好资料--18个VHDL实验源代码
- 20个VHDL实验源代码,包括: 1 交通灯控制器 2 格雷码变换器 3 BCD码加法器 4 四位全加器 5 四人抢答器 6 4位并行乘法器 9 步长可变加减计数器 10 可控脉冲发生器 11 正负脉宽数控信源 12 序列检测器 13 4位流水乘法器 14 出租车计费器 15 多功能数字钟 16 多功能数字秒表 17 频率计 18 七人表决器 19 数码锁 20 VGA彩条发生器
eda-chengxu
- VHDL语言源程序,使用元件例化的方法设计简易数字钟-VHDL language source code, the use of components instantiated designed simple digital clock
VHDL
- 数字钟的设计,有时,分,秒,置数等功能。-Digital clock design, sometimes, minutes and seconds, buy a few functions.
clock
- 完成数字钟表的功能,可以实现整点报时,闹钟和设置时间-The completion of the functions of digital watches, you can bring the whole point timekeeping, alarm clock and set-up times
timer
- VHDL语言设计的数字钟 具有时分秒三段显示-VHDL language designed with time-accurate digital clock shows three paragraphs
shizhong
- 数字钟的VHDL源程序,可以实现校时,校分等功能,并在试验箱上运行成功-The VHDL source code digital clock, you can achieve at school, school grade features, and success in the chamber is running on
EDAtest
- 关于数字钟的实现,用VHDL实现时,分,秒,的显示,并能报时-Digital clock on the realization of VHDL to achieve with hour, minute, seconds display, and time
EDA
- 以前学EDA的时候做过的四个小程序,分别是24/12小时制数字钟、数字频率计、乐曲播放电路、多人智力竞赛抢答器-EDA previously done when the four small procedures are 24/12 hour digital clock, digital frequency meter, circuit music players and many more devices quiz Answer
digital_clock_design
- 利用VHDL语言,逻辑器件设计CPLD,实现数字钟-Using VHDL language, design of logic devices CPLD, digital clock
shuzizhong
- 该数字钟可以实现3个功能:计时功能、整点报时功能和重置时间功能-The digital clock can achieve three functions: timing function, reset the whole hour and time functions
lcd_time
- 一个基于VHDL的多功能数字钟设计,能在LCD上显示时间,调整时间,整点报时,音乐为美妙的梁祝。-A VHDL-based design of multi-functional digital clock that can display time in the LCD, adjust the time, the whole point of time, music was wonderful Butterfly Lovers.
shuzizhong
- 数字电子钟设计,包括时、分、秒模块,文件中包括使用VHDL语言编写源码以及原理图(时、分、秒模块)(Digital clock source as well as schematic)
clock
- 数字钟可以实现整点响铃,预置数,十二小时24小时切换(Digital clock can achieve the whole point of the bell)
clock
- 用VHDL完成的数字钟设计。可选24h与12h两种时制,运用到按键消抖。(The digital clock is designed with VHDL. Optional 24h and 12h two kinds of time system, apply to the button to shake.)
szz
- 数字钟,24小时时制,每隔一分钟报时,每次两秒钟(A digital clock, ring lasts for two seconds per minute)